While the progress in the semiconductor integrated circuits reaches ULSI (ultra large scale integration) level or even higher level, the integrity of the integrated circuits rises at an amazing rate. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even to billions of devices. Taking DRAM (dynamic random access memories) for example, the increasing integrity in manufacturing extends the capacity of a single chip to step from earlier 4 megabit to 16 megabit, and further to 256 megabit or even higher. Integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within a smaller area without influencing the characteristics and operations of the integrated circuits.
The electrostatic discharge (ESD) zapping has became a serious problem as the feature size of the MOS transistor has been scaled down. A semiconductor device having the input/output pad connections with external circuitry and devices is subject to the problem of ESD. The ESD is easily conducted through the input/output and the power lead connections into the internal devices and causes some damage to the semiconductor devices, especially serious ones like gate oxide breakdown and damage caused by overheating.
The general IC products are required to endure the electrostatic discharge test of the human body model with two thousand volts and the machine model with two hundred volts. Therefore, for protecting the devices from ESD damage, built-in ESD protection circuits are connected between the input/output pads and the internal circuitry. The field-oxide device is one of the most used electrostatic discharged devices.
Referring to FIG. 1 and FIG. 2, the method to fabricate the field oxide device in deep submicron CMOS process is gradually changing from LOCOS (local oxidation of silicon) process in FIG. 1 to STI (shallow trench isolation) process in FIG. 2 because of the better isolation ability of the STI. However, the performance of the STI structure as ESD device is lowered due to the lower concentration in the interface of N.sup.+ 120, 124 and field implant 122 and causing the higher junction breakdown voltage of STI. Referring to FIG. 3, another ESD device with low V.sub.bd is the GGNMOS (gate grounded thin oxide NMOS). The ESD current path in the GGNMOS is near the surface of the substrate 136 and the heat dissipation is not easy. Moreover, the MOSFET has the LDD peak structure 130 which often focuses the ESD current discharged through the surface channel to cause a low ESD level.
Therefore, an ESD device with low junction breakdown voltage and free from heat dissipation near the surface channel is strongly requested. One new ESD structure is provided in the present invention with a deep current path to achieve these demands.